Design Of A Charge-Pump Based, Phase Locked Loop(Pll) For Medical Applications

Abstract

This paper presents the design and implementation of a low-power charge pump phase-locked loop (CP-PLL) intended for medical and biomedical electronic applications. The proposed PLL architecture consists of a phase frequency detector (PFD), charge pump (CP), loop filter (LF), voltage controlled oscillator (VCO), and frequency divider implemented in 90 nm CMOS technology. The system is designed to generate GHz-range output frequency from a MHz reference signal while maintaining low power consumption and reduced phase noise. A NAND/NOR based PFD is employed to minimize dead zone and blind zone issues, and a current-starved ring VCO is utilized for low power and wide tuning range. The proposed CP-PLL architecture is suitable for implantable and wearable medical devices where power efficiency and frequency stability are critical.