An Efficient VLSI Architecture for Pulse Shaping FIR Interpolation Filter of Multistandard DUC

Abstract

This work introduces an improved method for designing a pulse-shaping FIR interpolation filter used in multistandard DUC systems. The approach uses a two-stage optimization strategy specifically tailored for implementing a root-raised-cosine (RRC) interpolation filter. In the first stage, the goal is to cut down the number of multiplications and additions required for each input sample, which directly reduces hardware cost. The second stage applies the VHBCSE algorithm to build a more efficient constant-coefficient multiplier—the core building block of any FIR filter. This algorithm also helps streamline the multiplier–adder tree structure. To further boost speed, a carry-skip adder architecture is used in the accumulation unit. Overall, the proposed method results in a compact design that requires less silicon area and operates with lower power consumption.